Extremely anticipated: Whereas there is a Zen Three announcement inbound, we’re getting a number of key particulars forward of the October announcement due to leaked developer paperwork. Whereas this leak would not paint the entire image for what Zen Three goes to seem like, it suggests it needs to be one other robust CPU sequence for AMD with a number of generational enhancements.
Allegedly confidential paperwork have been leaked by Twitter person CyberPunkCat that appear to supply particulars on adjustments to Zen Three that can include the Ryzen 4000 desktop sequence, code named “Vermeer.”
We all know that AMD is taking the wraps off of Zen Three in October, and the small print discovered within the paperwork reiterate some issues we already know, whereas providing bits of latest info. The doc seems to be a Processor Programming Reference (PPR) for AMD’s Household 19h, Mannequin 21h B0, which might be Zen 3. Earlier Zen+ and Zen 2 architectures belong to AMD’s Household 17h, with varied fashions and revisions.
AMD normally makes this kind of documentation out there to builders after launch, so it is not precisely privileged info. Moreover, this type of developer paperwork are typically simply circulated — simply ask Intel.
Probably the most notable adjustments to Zen Three look like taking place within the CCD/CCX configuration. Zen Three will proceed to utilize a MCM (multi-chip module), or chiplet design, that can use two CCDs and one I/O die. There’ll solely be one CCX per CCD, and this CCX will encompass eight cores able to operating in both single-thread mode (1T) or two-thread SMT mode (2T). So, that is 16 complete threads per CCX.
This may occasionally recommend that Zen Three components will high out at 16 cores, in the identical style because the Ryzen 9 3950X. Although, we’ll have to attend and see as AMD might effectively have some methods up its sleeve.
Moreover, AMD is remodeling its cache subsystem. There will probably be a complete of 32MB of L3 cache (versus 16MB per CCX with Zen 2) shared throughout all eight cores within the CCX. Whereas Zen 2 provided 32MB of L3 cache per CCD, it needed to be shared between two separate complexes. There’s additionally 512KB of L2 cache per core inside the CCX, for a complete of 4MB of L2 cache per CCD.
Curiously, AMD can also be beefing up the Scalable Knowledge Cloth (SDF), which is the communication spine of Infinity Cloth answerable for the transport of knowledge and coherency between cores, reminiscence controllers, and different I/O components. The paperwork be aware that the SDF can now deal with 512GB per DRAM channel. It seems like there may be some minor adjustments to the Scalable Management Cloth (SCF), which is the opposite half of the Infinity Cloth that primarily handles signaling.
Elsewhere, Zen Three seems to be bulking up the reminiscence interface with two unified reminiscence controllers (UMC), with every supporting one DRAM channel and every channel supporting two DIMMs. There may even be help for DDR4-3200, which was natively supported with Zen 2. It seems like Zen Three will principally retain the identical options and connectivity for the Fusion Controller Hub (FCH) that have been current in Zen 2.
Along with some generational clock velocity bumps, it seems like Zen Three will additional polish AMD’s MCM strategy, specializing in bettering coherence and latency below the hood. We totally count on a measurable IPC enchancment over Zen 2 components as effectively.